1. Field of the Invention
The present invention relates generally to a semiconductor device and a fabrication process therefor. More specifically, the invention relates to a semiconductor device having an upper wiring layer provided with a bonding pad portion, and a fabrication process therefor.
2. Description of the Related Art
A semiconductor device fabricated on a silicon substrate includes a lower wiring layer (diffusion layer, lower layer wiring and so forth) formed in the silicon substrate surface or on the silicon substrate, an interlayer insulation layer covering the lower wiring layer, a connection hole (contact hole) formed through the interlayer insulation layer and extending to the lower wiring layer, an upper wiring layer, a surface protection layer covering the upper wiring layer and the interlayer insulation layer and a bonding pad portion including an opening formed in the surface protection layer and extending to the upper wiring layer. The semiconductor elements are formed only with the diffusion layer (in this case, the lower wiring layer is formed with only diffusion layer) or the diffusion layer and the lower wiring layer (in this case, the lower wiring layer is formed with the diffusion layer and the lower wiring layer). In the case where the lower wiring layer is formed with the diffusion layer and the lower wiring layer, a contact hole connecting the upper wiring layer and the lower wiring layer includes a contact hole connecting at least the upper and lower wiring layers. The semiconductor device is mounted in a package and electrically connected to a plurality of external lead portions of the package. A plurality of bonding pad portions provided in the upper wiring layer have a size of approximately 100 .mu.m of length in each edge, and connected to respective external lead portions by bonding lines formed with aluminum wire or gold wire.
For realizing high package density of the semiconductor device, the wire widths of upper layer wiring and so forth are reduced. Associating therewith, in the bottom of the contact hole, a barrier layer is formed between the upper wiring layer and the lower wiring layer. This is for controlling mutual diffusion of conductive materials forming the upper wiring layer and the lower wiring layer. On the other hand, the upper layer wiring primarily formed of an aluminum or aluminum alloy is constituted of a stacked film of a film of a refractory metal or refractory metal alloy and a film of aluminum or aluminum alloy for improving stress migration strength (and electro-migration strength). In this case, the high melting metal film or the refractory metal alloy is directly in contact with the interlayer insulation layer.
In the upper wiring layer having the stacked structure as set forth above, special attention becomes necessary for connection of the bonding wire (of aluminum wire or gold wire) for connecting the external lead portions to the bonding pad portions. This is because low bonding ability between the interlayer insulation layer and the refractory metal film or refractory metal alloy film. Namely, when connection of the bonding wire is performed with applying ultrasonic vibration to the bonding pad portion, the upper wiring layer at the corresponding portion tends to be peeled off from the interlayer insulation layer. One solution for this problem is disclosed in Japanese Unexamined Patent Publication (Kokai) No. Heisei 3-127843.
FIG. 1 shows a section of a semiconductor device disclosed in the above-identified publication. As shown in FIG. 1, on the surface of a semiconductor substrate 401, a field oxide layer 402 is formed. An interlayer insulation layer covering the field oxide layer 402 is formed with stacked films of a BPSG film 431 directly covering the field oxide layer 402 and a TEOS oxide film 433 formed on the BPSG film 431. On this interlayer insulation layer, an upper wiring pattern or upper wiring layer is formed. The upper wiring is constituted of a stacked film of a titanium nitride film 441 directly contacting with the upper surface of the TEOS oxide film 433 and an aluminum film 443. The upper wiring is covered with a surface protective layer 451. A part of the surface protective layer 451 above the upper wiring is locally removed to define an opening to access the aluminum film 443. With the opening reaching the aluminum film 443 formed through the surface protective layer 451, bonding pad portion 456 is formed.
With the construction set forth above, upon connection of the bonding wire, peeling off of the upper wiring from the interlayer insulation layer can be successfully prevented. Also, it is discussed in the publication that, by forming the upper film portion of the interlayer insulation layer with TEOS oxide layer 433, firm fitting ability of the titanium nitride film 441 and the interlayer insulation layer can be improved.
In the semiconductor device disclosed in the above-identified publication, the problem of peeling off of the upper wiring from the interlayer insulation layer upon connection of the bonding wire to the bonding pad portion of the upper wiring, can be solved. In this case, in the bottom of the contact hole provided in the interlayer insulation layer and extending to the lower wiring layer, the titanium nitride film forming the upper wiring directly contacts with the lower layer wiring. However, in the upper wiring of the construction set forth above, a contact resistance between the upper wiring and the lower wiring connected through the contact hole becomes greater, on the order of hundreds of times than that in the case where no titanium nitride film is present.
As a method for suppressing increasing of the contact resistance, it has been considered to take a method for forming the upper wiring in the construction at least including a stacked film consisted of three layers of titanium film directly contacting with the upper surface of the interlayer insulation layer, the titanium nitride film and aluminum film or aluminum alloy film. In the stacked three layer structure of the upper wiring as set forth above, in the bottom of the contact hole formed in the interlayer insulation layer and extending to the lower wiring layer, the titanium film forming the upper wiring or titanium alloy film of titanium and the conductive material forming the lower wiring directly contacts the lower wiring layer, and the titanium nitride is not directly contacted with the lower wiring layer. Therefore, increasing of the contact resistance can be limited. However, in the upper wiring including such stacked three layer structure, the problem that the upper wiring tends to peel off the interlayer insulation layer upon connection of the bonding wire to the bonding pad of the upper wiring, becomes significant.
The inventors have reported in 1993, Spring, 40th Applied Physics United Lecture Meeting, Lecture Paper, pp 671 (Lecture No. 29p-ZY-3) about a cause which makes the upper wiring to be easily peeled off the interlayer insulation layer upon connecting the bonding wire to the bonding pad portion in the upper wiring including the above-mentioned three layer structure.
Here, method of measurement of direct peeling was according to MIL specification, method 2011.4 bonding strength (destructive bond tensile test). The interlayer insulation layers were the following three kinds.
A: BPSG film formed by a low pressure CVD method (LPCVD method) with taking TEOS as one of materials; PA1 B: silicon oxide film formed by a plasma CVD method with taking TEOS as one of materials; and PA1 C: silicon oxide film formed by a plasma CVD method with taking silane type gas and dinitrogen monoxide gas. PA1 A: BPSG film formed by a low pressure CVD method (LPCVD method) with taking TEOS as one of the materials; PA1 B: silicon oxide film formed by a plasma CVD method with taking TEOS as one of the materials; and PA1 C: silicon oxide film formed by a plasma CVD method with taking silane type gas and dinitrogen monoxide gas. PA1 a silicon substrate having a field oxide layer which is selectively formed; PA1 a lower wiring layer provided on at least the surface of the silicon substrate; PA1 an interlayer insulation layer covering the silicon substrate and the lower wiring layer and having a connection hole formed at a predetermined position and extending to the lower wiring layer: PA1 an upper wiring having a stacked structure at least including first titanium nitride film directly covering the upper surface of the interlayer insulation layer, a titanium film, a second titanium nitride film and an aluminum or aluminum alloy film, on the interlayer insulation layer, and one of a stacked structure at least including the titanium film, the second titanium nitride film and the aluminum or aluminum alloy film, a stacked structure at least including a titanium alloy film, the second titanium nitride film and the aluminum or aluminum alloy film and a stacked structure at least including the titanium alloy film, the titanium film, the second titanium nitride film and the aluminum or aluminum alloy film; PA1 a surface protection layer covering the interlayer insulation layer and the upper wiring; and PA1 a bonding pad portion constituted of an opening provided through the surface protection layer and reaching to the upper wiring and the portion of the upper wiring exposed through the opening. PA1 forming a field oxide layer on the surface of a silicon substrate; PA1 forming a lower wiring layer at least on the surface of the silicon substrate; PA1 forming an interlayer insulation layer covering the silicon substrate and the lower wiring layer, and forming a first titanium nitride film covering the interlayer insulation layer; PA1 sequentially performing etching sequentially for the first titanium nitride film and the interlayer insulation layer at a predetermined position for forming a connection hole extending to the lower wiring layer; PA1 forming a titanium film and a second titanium nitride film in order over the entire surface and further forming at least an aluminum or aluminum alloy film over the entire surface; PA1 performing etching at least for the aluminum or aluminum alloy film and further sequentially performing for the second titanium nitride film, the titanium film and the first titanium nitride film for forming an upper wiring; and PA1 forming a surface protection layer over the entire surface and performing etching at a predetermined position to form an opening reaching to the upper wiring. PA1 forming a field oxide layer on the surface of a silicon substrate; PA1 forming a lower wiring layer at least on the surface of the silicon substrate; PA1 forming an interlayer insulation layer of a silicon oxide film formed by way of plasma CVD method with materials of silane type gas and dinitrogen monoxide gas at least over the entire surface; PA1 processing the upper surface of the interlayer insulation layer by plasma; PA1 performing etching for the interlayer insulation layer at a predetermined position for forming a connection hole extending to the lower wiring layer; PA1 forming a titanium film and a titanium nitride film in order over the entire surface and further forming at least an aluminum or aluminum alloy film over the entire surface; PA1 performing etching at least for the aluminum or aluminum alloy film and further sequentially performing for the second titanium nitride film and, the titanium film for forming an upper wiring; and PA1 forming a surface protection layer over the entire surface and performing etching at a predetermined position to form an opening reaching to the upper wiring. PA1 forming a field oxide layer on the surface of a silicon substrate; PA1 forming a lower wiring layer at least on the surface of the silicon substrate; PA1 forming an interlayer insulation layer of a silicon oxide film formed by way of plasma CVD method with materials of silane type gas and dinitrogen monoxide gas at least over the entire surface; PA1 performing etching for the interlayer insulation layer at a predetermined position for forming a connection hole extending to the lower wiring layer; PA1 forming a titanium film and a titanium nitride film in order over the entire surface and further forming at least an aluminum or aluminum alloy film over the entire surface; PA1 performing etching at least for the aluminum or aluminum alloy film and further sequentially performing for the second titanium nitride film and, the titanium film for forming an upper wiring; and PA1 forming a surface protection layer over the entire surface and performing etching at a predetermined position to form an opening reaching to the upper wiring.
On the other hand, as the bonding wire, aluminum wire was employed. Also, as the bonding method, an ultrasonic bonding was employed.
With respect to samples thus obtained, rate of occurrence of peeling off was compared with the method set forth above, then, the result, A:B:C=7.1%:0.7%:0.0% was obtained. The peeling off occurring rate is closely associated with the load upon occurrence of peeling off in the scratch test. The inventors have attained the conclusion that practically no problem will arise if the load upon occurrence of peeling off is greater than or equal to 53 g in the scratch test.
In the additional test performed by the inventors, in the construction of the semiconductor device disclosed in the above-identified publication, when the upper wiring is provided directly on the BPSG film, namely when the interlayer insulation layer is formed with only BPSG film, the load upon occurrence of peeling off in the scratch test becomes greater than or equal to 90 g. Therefore, no problem will arise in practical use.
FIG. 2 is a section of the semiconductor device showing the structure of the sample used in the scratch test and so forth in the foregoing report. As shown in FIG. 2, on a P-type silicon substrate 501, a field oxide layer 502 is formed. The field oxide layer 502 is covered with an interlayer insulation layer 531 having a thickness of 600 nm. The interlayer insulation layer 531 is the following three kinds similarly to the sample used for checking the peeling off occurring rate.
After forming the samples of the structure as set forth above, rapid thermal annealing (RTA) was performed by heating at 650.degree. C. for 30 seconds, then the scratch test was performed. Comparing the load upon occurrence of peeling off depending upon difference of the interlayer insulation layer, the result, A:B:C=4.00 g:50.2 g:63.8 g was obtained.
Measuring the interfaces between the titanium layers 542 and the interlayer insulation layers 531 of the samples of the structures as set forth above by way of X-ray electron spectroscopy (XPS), the result was obtained that titanium oxide (TiO.sub.x (x=2-.alpha.) was present, and the number of count per one second of this TiO.sub.x depends upon the composition of the interlayer insulation layer.
FIG. 3 is a graph showing a relationship between the XPS intensity of TiO.sub.x and load at occurrence of peeling off in the scratch test. As can be seen from FIG. 3, smaller amount of TiO.sub.x at the interface between the titanium film 542 and the interlayer insulation layer 531 results in greater load at the occurrence of peeling off in the scratch test.